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L6393
Half-bridge gate driver
Preliminary Data
Features

High voltage rail up to 600 V dV/dt immunity 50 V/nsec in full temperature range Driver current capability: - 270 mA source, - 430 mA sink Switching times 75/35 nsec rise/fall with 1 nF load 3.3 V, 5 V CMOS/TTL inputs comparators with hysteresys Integrated bootstrap diode Uncommitted comparator Adjustable dead-time Compact and simplified layout Bill of material reduction Flexible, easy and fast design
SO-14

DIP-14
Description
The L6393 is a high-voltage device manufactured with the BCD "OFF-LINE" technology. It has a monolithic half-bridge gate driver for N-channel Power MOSFET or IGBT. The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy of interfacing C/DSP. The IC embeds an uncommited comparator available for protections against over-current, over-temperature, etc.
Application
Motor driver for home appliances, factory automation, industrial drives and fans. HID ballasts, power supply units.
Table 1.
Device summary
Order codes L6393 L6393D L6393D013TR Package DIP-14 SO-14 SO-14 Packaging Tube Tube Tape and reel
March 2008
Rev 2
1/20
www.st.com 20
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
L6393
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 4
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 4.2 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 5.2 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 7 8
Waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
L6393
Block diagram
1
Block diagram
Figure 1.
VCC 4 UV DETECTION
Block diagram
BOOTSTRAPDRIVER FLOATINGSTRUCTURE 14
BOOT
from LVG
UV DETECTION S R HVG DRIVER 13 HVG
PHASE
1
LEVEL SHIFTER
LOGIC BRAKE 3 SHOOT THROUGH PREVENTION VCC 2 LVG DRIVER
12
OUT
SD
LVG 10
CPOUT
6 COMPARATOR
5V + -
10 9 8 CP+ CP-
DT
5
DEAD TIME
GND
7
3/20
Pin connection
L6393
2
Pin connection
Figure 2. Pin connection (top view)
PHASE SD BRAKE VCC DT CPOUT GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 BOOT HVG OUT NC LVG CP+ CP-
2.1
Pin description
Table 2.
Pin N# 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin description
Pin name PHASE SD
(1)
Type I I I P I O P I I O
Function Driver logic input (active high) Shut down input (active low) Driver logic input (active low) Lower section supply voltage Dead time setting Comparator output (open drain) Ground Comparator negative input Comparator positive input Low side driver output Not connected
BRAKE VCC DT CPOUT GND CPCP+ LVG
(1)
NC OUT HVG
(1)
P O P
High side (floating) common voltage High side driver output Bootstrapped supply voltage
BOOT
1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/20
L6393
Truth table
3
Truth table
Table 3. Truth table
INPUTS SD L H H H H PHASE X L L H H BRAKE X L H L H LVG L H H H L OUTPUTS HVG L L L L H
Note:
X: don't care In the L6393 IC the two input signals PHASE and BRAKE are fed into an AND logic port and the resulting signal is in phase with the high side output HVG and in opposition of phase with the low side output LVG. This means that if BRAKE is kept to high level, the PHASE signal drives the half-bridge in phase with the HVG output and in opposition of phase with the LVG output. If BRAKE is set to low level the low side output LVG is always ON and the high side output HVG is always OFF, whatever the PHASE signal. This kind of logic interface provides the possibility to control the power stages using the PHASE signal to select the current direction in the bridge and the BRAKE signal to perform current slow decay on the low sides. From the point of view of the logic operations the two signals PHASE and BRAKE are completely equivalent, that means the two signals can be exchanged without any change in the behavior on the resulting output signals (see the Block Diagram in Fig.1). Note: the dead time between the turn OFF of one power switch and the turn ON of the other power switch is defined by the resistor connected between DT pin and the ground.
5/20
Electrical data
L6393
4
4.1
Electrical data
Absolute maximum ratings
Table 4.
Symbol Vout Vcc VcpVcp+ Vboot Vhvg VIvg Vi Vcpout
Absolute maximum rating
Parameter Output voltage Supply voltage Comparator negative input voltage Comparator positive input voltage Floating supply voltage High side gate output voltage output voltage High side gate output voltage output voltage Logic input voltage Open drain voltage Value Vboot - 21 to Vboot + 0.3 - 0.3 to + 21 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 VCC - 0.3 to 620 Vout - 0.3 to Vboot + 0.3 -0.3 to Vcc +0.3 -0.3 to 15 -0.3 to 15 50 TBD 150 -50 to 150 Unit V V V V V V V V V V/ns mW C C
dVout/dt Allowed output slew rate Ptot TJ Tstg Total power dissipation (TA = 85 C) Junction temperature Storage temperature
Note:
ESD immunity for pins 12, 13 and 14 is guaranteed up to V (Human Body Model)
4.2
Thermal data
Table 5.
Symbol Rth(JA)
Thermal data
Parameter Thermal resistance junction to ambient max. SO-14 165 DIP-14 100 Unit C/W
6/20
L6393
Electrical data
4.3
Recommended operating conditions
Table 6. Recommended operating conditions
Parameter
(1)
Symbol Pin Vout VBS (2) fsw Vcc
Tj
Test condition
Min
Max 580
Unit V V kHz V C
12 Output voltage
14 Floating supply voltage (1) Switching frequency 4 Supply Voltage Junction Temperature HVG, LVG load CL = 1 nF
TBD
TBD 800
TBD 40
TBD 125
1. If the condition TBD V < Vboot - Vout < TBD V and Vboot < TBD V are guaranteed, Vout can range from TBD V to 580 V 2. VBS = Vboot -Vout
7/20
Electrical characteristics
L6393
5
5.1
Table 7.
Symbol
Electrical characteristics
AC operation
AC operation electrical characteristics (VCC = 15 V, TJ = +25 C)
Pin Parameter Test condition Min Typ Max Unit
AC operation ton toff 1,3 vs 10, 13 High/low side driver turnon propagation delay High/low side driver turnoff propagation delay 125 125 ns ns
tsd
2 vs Shut down to high/low 10, side propagation delay 13 Delay matching, HS & LS turn-ON/OFF
Vout = 0 V Vboot = Vcc CL = 1 nF Vi = 0 to 3.3 V see Figure 3 on page 9
125
ns
MT
40 Rdt = 0, CL = 1 nF, CDT = 100 nF Rdt = 37 k, CL = 1 nF, CDT = 100 nF Rdt = 136 k, CL = 1 nF, CDT = 100 nF Rdt = 260 k, CL = 1 nF, CDT = 100 nF Rdt = 0 ; CL = 1 nF; CDT = 100 nF Rdt = 37 k;CL = 1 nF;CDT = 100 nF Rd = 136 k;CL = 1 nF;CDT = 100 nF Rdt = 260 k;CL = 1 nF;CDT = 100 nF CL = 1000 pF CL = 1000 pF 75 35 0.15 0.5 1.5 2.8 60 TBD TBD TBD
ns s s s s ns ns ns ns ns ns
dt
5
Dead time setting range
MDT
Matching dead time
tr tf
10, 13
Rise time Fall time
8/20
L6393 Figure 3. Timing
Logic Input
(PHASE or BRAKE)
50% 50%
Electrical characteristics
tr
90% 90%
tf
HVG
ton
10%
10%
toff
Logic Input
(PHASE or BRAKE)
50%
50%
tf
90%
tr
90% 10% 10%
LVG
toff
ton
SD
50%
50%
tr
90% 90%
tf
LVG/HVG
ton
10%
10%
toff
9/20
Electrical characteristics
L6393
5.2
Table 8.
Symbol
DC operation
DC opereation electrical characteristics (VCC = 15 V; TJ = +25 C)
Pin Parameter Test condition Min Typ Max Unit
Low supply voltage section Vcc_hys Vcc_thON Vcc_thOFF Vcc UV hysteresis Vcc UV Turn ON threshold Vcc UV Turn OFF threshold VCC = 8 V SD = 5 V; PHASE and BRAKE = GND; RDT = 0 ; CP + = GND; CP - = 0.5 V VCC = 15 V SD = 5 V; PHASE and BRAKE = GND; RDT = 0 ; CP + = GND; CP - = 0.5 V 600 1500 9.5 8.0 mV V V
Iqccu
4
Undervoltage quiescent supply current
110
150
A
Iqcc
Quiescent current
600
1000
A
Bootstrapped supply voltage section VBS_hys VBS_thON VBS_thOFF VBS UV hysteresis VBS UV turn ON Threshold VBS UV turn OFF Threshold VBS = 7 V SD = 5 V; PHASE and BRAKE = 5 V; RDT = 0 ; CP + = GND; CP - = 0.5 V VBS = 15 V SD = 5 V; PHASE and BRAKE = 5 V; RDT = 0 ; CP + = GND; CP - = 0.5 V Vhvg = Vout = Vboot = 600 V LVG ON 120 600 1000 9.1 8.1 mV V V
IQBSU
14
Undervoltage Vboot quiescent current
60
110
A
IQBS
Vboot quiescent current
140
210
A
ILK Rdson
High voltage leakage current Bootstrap driver on resistance (1)
10
A
10/20
L6393 Table 8.
Symbol
Electrical characteristics DC opereation electrical characteristics (VCC = 15 V; TJ = +25 C) (continued)
Pin Parameter Test condition Min Typ Max Unit
Driving buffers section Iso 10, 13 Isi Logic inputs Vil 1, 2, 3 Vih IPHASEh 1 IPHASEl IBRAKEh 3 IBRAKEl ISDh 2 ISDl SD logic "0" input bias current SD = 0 V 1 A BRAKE logic "0" input bias BRAKE = 0 V current SD logic "1" input bias current SD = 15 V 30 1 100 A A PHASE logic "0" input bias PHASE = 0 V current BRAKE logic "1" input bias BRAKE = 15 V current 175 1 260 A A High level logic threshold voltage PHASE logic "1" input bias PHASE = 15 V current 2.21 175 260 V A Low level logic threshold voltage 0.83 V High/low side sink short circuit current VIN = Vil (tp < 10 s) 430 mA High/low side source short VIN = Vih (tp < 10 s) circuit current 270 mA
1. RDSon is tested in the following way: RDSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.
Table 9.
Symbol Vio Iib Vol td_comp SR
Sense comparator
Pin 8, 9 Input bias current 6 Open drain low level Output voltage Comparator delay 6 Slew rate Iod = - 3 mA CPOUT pulled to 5 V through 100k resistor CL = 180 nF, Rpu = 5 k 110 TBD 1 0.5 210 Parameter Input offset voltage Test conditions Min Typ 10 Max TBD Unit mV A V ns V/s
11/20
Waveforms definition
L6393
6
Figure 4.
PHASE BRAKE
Waveforms definition
Dead time waveform definition
LVG DT HVG DT DT DT
12/20
L6393
Typical application diagram
7
Figure 5.
VCC
Typical application diagram
Application diagram
BOOTSTRAP DRIVER FLOATING STRUCTURE 14 BOOT
4 UV DETECTION
from LVG
UV DETECTION S R HVG DRIVER 13 HVG
H.V.
Cboot
PHASE
1
LEVEL SHIFTER
LOGIC BRAKE 3 SHOOT THROUGH PREVENTION VCC SD 2 10 CPOUT 6 COMPARATOR 5V + 10 9 8 CP+ CPLVG DRIVER
12
OUT TO LOAD LVG
DT
5
DEAD TIME
GND
7
13/20
Bootstrap driver
L6393
8
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 6.a). In the L6393 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure 6.b. An internal charge pump (Figure 6.b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it.
8.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge:
Q gate C EXT = ------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be:
CBOOT >>> CEXT e.g.: if Qgate is 30nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. e.g.: HVG steady state consumption is lower than 200 A, so if HVG TON is 5 ms, CBOOT has to supply 1 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 1 V. The internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value: 120 ). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS:
Q gate V drop = I ch arg e R dson V drop = ------------------ R dson T ch arg e
14/20
L6393
Bootstrap driver where Qgate is the gate charge of the external power MOS, RDSon is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30 nC the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact:
30nC V drop = -------------- 120 0.7V 5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used. Figure 6. Bootstrap driver
DBOOT
VS
BOOT H.V. HVG
VS
BOOT H.V. HVG
CBOOT VOUT TO LOAD
CBOOT VOUT TO LOAD
LVG
LVG
a
b
D99IN1067
15/20
Package mechanical data
L6393
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
16/20
L6393 Figure 7.
DIM. MIN. a1 B b b1 D E e e3 F I L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65
Package mechanical data DIP-14 mechanical data and package dimensions
mm TYP. MAX. MIN. 0.020 0.055 0.020 0.010 0.787 0.065 inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
DIP-14
0.100
17/20
Package mechanical data Figure 8. SO-14 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 B C D
(1)
L6393
inch MAX. 1.75 0.30 1.65 0.51 0.25 8.75 4.0 MIN. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 6.20 0.50 1.27 0.228 0.01 0.016 0.244 0.02 0.050 TYP. MAX. 0.069 0.012 0.065 0.020 0.01 0.344 0.157
TYP.
OUTLINE AND MECHANICAL DATA
1.35 0.10 1.10 0.33 0.19 8.55 3.80 1.27 5.8 0.25 0.40
E e H h L k ddd
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO-14
0016019 D
18/20
L6393
Revision history
10
Revision history
Table 10.
Date 03-Mar-2008 18-Mar-2008
Document revision history
Revision 1 2 Initial release Cover page updated Changes
19/20
L6393
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